LabVIEW-Based Detection System Memory （part 1）

LabVIEW-Based Detection System Memory （part 1）




Abstract: According to an equipment storage without the corresponding test equipment, the test is relatively more complicated design of the memory-based LabVlEW detection system. PXI hardware, relying on test bus to achieve it. High reliability. Strong flexibility characteristics. Memory for the combination of features, design a dedicated interface laptop adapter is mainly used for signal synchronization and conditioning. This paper analyzes the type of memory failure, study and had extended March algorithm. LabVIEW as a software tool system to achieve automated testing of memory, using the database to achieve the test method and test procedures for separation. The system has easy to use, scalability and other properties, effectively improved the memory of a test efficiency equipment.

Key words: memory; virtual instruments; LabVIEW; database; March



In the electronic equipment during operation, memory failure or failure, not only led to economic losses, but also may lead to disastrous consequences. Therefore, memory testing has also become an important issue in today's world, in the military equipment in the memory is playing a very important role. At present, based on virtual instrument designed for automated test systems have become mainstream, while the software is the core of the virtual instrument. At this point, with LabVIEW as software tools, combined with the corresponding figures I / O cards, develop a set of memory testing equipment used in a detection system.



An overall program and hardware design

1.1 Requirements Analysis

The system tested the selected object is a certain type of equipment in the common memory, the test channel with address bus 18, data bus 18, control line 3 (line of control in a total of seven, including three valid). Among them, the status output signal, said read / write signals are effective; read / write signal, said right RAM read / write operations; data output valid signal, said data output is valid. Capacity of 8 KB, read cycle, 400 ns, the write cycle 500 ns, power supply voltage of 5 V.

1.2 Hardware Design

The hardware system to the computer center as the main body, to insert one of the digital I / O cards feature. Through computer-controlled digital I / O cards for digital signal output and measurement. It can be seen, the system platform to build the key is to select the appropriate number of I / O cards. The system tests the main signals are address signals, data signals and control signals. Taking into account the output bits and speed of the company with the NI digital waveform generator / analyzer 6542, which has 32 bi-directional control channel can be easily signal output and signal acquisition. The module for each channel 1 Mb, 8 Mb and 64 Mb of onboard memory, easy to test the information storage.

1.3 interface laptop adapter design and port allocation

Interface laptop adapter for connecting the device under test and test platforms. Design-time use only one 6542 module, so only 32 output channels, can not be achieved effectively simultaneous output of all signals designed to be applied for data lines and address lines of the principle of sharing to be addressed. Interface Laptop Adapter the composition of the block diagram shown in Figure 1. Select 6542's portO ~ port2 as the common address lines and data lines, port3 as the Line of Control. A two-way latch latch select, through the directional control latch data input / output chip select control line control data latches, latch output control line control latch inside the data read-out.



2 Memory Test Algorithm Analysis

2.1 Memory Fault Type

Memory failure in general can be divided into a single unit failures and failures between the two types of cells. A single unit failure include: viscous fault (SAF) an array is always 0 or 1; conversion failure (TF), that is, a specific unit in a certain sequence of conversion can not be 0 / 1 turnover; data retention fault (DFR), that is, a unit in a period of time can not keep its logic value, etc.. Unit is mainly between the failure of coupling fault (CF), which includes the word within a word between failures and faults.



2.2. Algorithm March

Failure for the different types of memory, made a variety of memory test algorithms, such as March algorithms, Walking algorithm, Calloping algorithm. One, March algorithm has higher fault coverage, smaller time complexity, in the memory test to be widely used. The basic steps to use formula is as follows:

Where: Cij represents the first i row, j-column memory cell; R is a read operation; W is a write operation; that the set of all C; Σ said that the sum of episodes; comma "," is the formula for the orderly operation between the separator; 0 or 1, said background data and operational data. Formula can be calculated according to the test complexity is 5N. Simple terms it is in accordance with certain rules to memory write and read data. For different fault models, test different data backgrounds to add the corresponding fault coverage can be achieved. Usually, an algorithm can not cover all of the fault type, so the test to use two or more algorithms.

2.3 March algorithm to detect System

March algorithms are generally operate in bits, while the measured object is 18-bit data path, storage means for storing bytes, and should therefore be extended to the March algorithm. Tests to take into account not only the inter-word fault, but also should be considered a multiple-bit words of the coupling between the fault. Faced with this situation should increase the test data March algorithms. For the N bits of memory, a total of log2N +1 kinds of test data, literature data are given background formula. The measured object has 18-bit memory, there are five groups by calculating the test data:



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